The present invention relates to a data processing system including a host system, an input/output device and a communication control system which operates to control data transfer between the host system and the input/output device.
In a communication control system, such as a disk controller, there are both a portion which is operated in response to a first clock signal to which the host system responds and a portion which is operated in response to a second clock signal to which an input/output device such as a disk device responds.
FIG. 1 is an internal block diagram of a prior art data processor including such a communication control system 101 which contains a first-in first-out ("FIFO") register 102, a first processor 103, a synchronizing circuit 104, a second processor 105, and a group of registers 106. The comunication control system 101 is connected to a host system 100 by a bus 107, and to an external input/outut device 120 by a line 108.
The host system 100 includes a host processor 110, a direct memory access circuit (DMAC) 112, and a random access memory (RAM) 114. The decoder 116 is provided to decode an address on the bus 107 to start the operation of the first processor 103 when the decoded address is for the first processor.
When a macrocommand is issued from the host system 100, the first processor 103 decodes and converts it into a combination of lower-level commands, and issues each command to the second processor 105 by way of the bus 204 after it has stored in the group of registers 106 control parameters necessary for the second processor 105 to execute that command.
A start signal is provided to a synchronizing circuit 104 by the first processor 103 to order the second processor 105 to execute the command. The start signal is changed into a signal which is synchronized with the second clock signal which controls the second processor 105 by the synchronizing circuit 104 and is supplied to the second processor 105. The second processor 105 reads out the contents of the group of registers 106 and executes a command to read data from the input/output device 120 based upon the contents of the registers 106 and to write the read out data into FIFO 102, the first processor 103 starts reading data from FIFO 102 in parallel to the writing operation being performed by the second processor 105, thereby to send the read out data to the data buffer 109 by way of the bus 107. After completion of writing of a block of data into the data buffer 109, the DMAC 112 transfers the block of data to the RAM 114.
The necessity of FIFO 102 will be explained below. If we modify the circuit in FIG. 1 so that the FIFO 102 is removed and the data read out of the input/output device 120 is directly written into the data buffer 109 by way of the lines 107, the following problem will arise. During the time a block of data is being written into the data buffer 109 by the second processor 105, it may occur that the host processor 110 requires the bus 107, for example, in order to refresh RAM 114 when it is in the form of a dynamic memory. Therefore, the bus 107 cannot be used at that time for writng data into the data buffer 109. The FIFO 102 is provided so that the data sequentially read out of the input/output device 120 may be temporarily held by FIFO 102 until the bus 107 becomes available again for transmission of the read out data to the data buffer 109 on the line 107.
Therefore, the FIFO must operate at a high speed so that the read operation from the FIFO and the write operation into the FIFO must be effected in response to different clocks. This makes the circuit configuration of the FIFO complicated.